Introduction
The hardware team in Boeblingen develops the most powerful server systems in the world – in an international work environment with our partner labs in the USA, Israel and India. We are using modern verification methods and are continuously optimizing our development processes.

Your Role and Responsibilities
We are offering an Bachelor- or Master-Thesis: Enabling an open-source verification flow for IBM processors

To develop complex microprocessors, multiple hierarchies of the design are being simulated in order to ensure a first-time right design when the first chips are being produced. These complex chips consisting of ASICS and processors incorporate IP as well as standard interfaces. The current IBM verification framework consists of proprietary tools from EDA vendors as well as internal tools. To enable horizontal and vertical reuse across multiple verification levels and components, it is important to base the verification methodology on standards such as Portable Stimulus, languages such as System Verilog but also enabling common programming languages such as Python and C++.

The goal of this master thesis is to enable a verification workflow which is taking advantage of open-source developments as much as possible. One step that has already been taken is to integrate the most popular open-source verification framework CocoTB into the verification methodology. But there is much more to be enabled as part of this thesis. More specifically we would like to evaluate the capabilities of Verilator, an open-source simulator https://github.com/verilator/verilator to understand how this tool can potentially augment and shape IBM’s future verification methodology.

A first step is to compare the performance of the Verilator against that of in-house simulators. Moreover – given the complexity and size of IBM hardware designs – scalability is another major factor. Based on the results and experience obtained from first test runs there are many other aspects to investigate – such as exploring if Verilator can directly be integrated into our IBM verification environments to enable SystemVerilog simulation alongside with our new designs.

If you are interested to work very close to the micro-architecture and the functionality of a design, developing great user experiences for hardware development – this is the place to be!

If you’re interested please get in contact with us and include in your response all relevant documents (preferably all in one single pdf file):

1. Cover Letter incl. your availability (earliest start and latest end date)
2. CV incl. your level of German
3. Certificate of enrollment from you university
4. Current transcript of records and other relevant certificates / references
5. Non-EU citizen studying in Germany: copy of passport, residence and work permit
6. Non-EU citizen studying elsewhere: prove of identity incl. place of birth

We are looking forward to your application !

Required Technical and Professional Expertise

• Study of computer science, electrical engineering or a similar direction
• Good knowledge of programming, knowledge of a scripting language like Python
• Knowledge of Development tools / technologies (e.g. git)
• Good team worker and interest to work in international teams
• Strong abilities in communication in English

Preferred Technical and Professional Expertise
First experience in developing hardware, e.g. VHDL or Verilog knowledge