Introduction
The High Speed IO design team delivers both proprietary and industry standard interfaces for IBM’s POWER systems’ and Z Mainframe’s processors. With a current data rate up to 64Gbps and rising, verifying the functionality of the digital and analog components in an efficient manner is necessary.

Your Role and Responsibilities

• Understand the design specification, Power On Specification, and Power management specification.
• Understand boot firmware and reset flow. And/or Power management flow.
• Develop skills in IBM BIST verification tools and apply them successfully
• Develop the verification environment and test bench
• Debug fails using waveform, trace tools and debug RTL code
• Work with Design team in resolving/debugging logic design issues and responsible for deliveries

Required Technical and Professional Expertise

• Experience in Design Verification – demonstrated execution experience of verification of logic blocks
• Strong in SoC verification: Chip reset sequence and initialization, and/or Power management.
• Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL)
• Good programming skills in C/C++, Python/Perl
• Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails
• Hardware debug skills backed by relevant experience on projects
• Exposure in developing testbench environment, write complex test scenarios
• Good communication skills and be able to work effectively in a global team environment
• Drive verification coverage closure

Preferred Technical and Professional Expertise

• Knowledge of Chip-Initialisation , SCAN , BIST is a plus
• Scripting Expertise backed up relevant experience in the same
• Writing Verification test plans
• Functional and code coverage analysis and debug